Regviz

Silicon Labs /EFR32ZG23B020F512IM40 /DPLL0_S /CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/DPLL0_S/CFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FLL)MODE 0 (EDGESEL)EDGESEL 0 (AUTORECOVER)AUTORECOVER 0 (DITHEN)DITHEN

MODE=FLL

Description

No Description

Fields

MODE

Operating Mode Control

0 (FLL): Frequency Lock Mode

1 (PLL): Phase Lock Mode
EDGESEL

Reference Edge Select
AUTORECOVER

Automatic Recovery Control
DITHEN

Dither Enable Control

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data